Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability

Authors:
P. Benoit;G. Sassatelli;L. Torres;D. Demigny;M. Robert;G. Cambon
Affiliations:
-;-;-;-;-;-
Venue:
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Year:
2003

Citing 0
Cited 5

Generic Design Space Exploration for Reconfigurable Architectures

IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing

Microprocessors & Microsystems
Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths

Integration, the VLSI Journal
Power, performance and security optimized hardware design for H.264

Proceedings of the Sixth Annual Workshop on Cyber Security and Information Intelligence Research
Design space exploration for low-power reconfigurable fabrics

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing

Quantified Score

Hi-index	0.00

Visualization

Abstract

More and more reconfigurable architectures are today available as IP cores for SoC designers. These ones often differ according to several parameters (granularity, reconfiguration mode, topology驴). Therefore, it is not straightforward to compare different architectures and choose the right one considering a given set of requirements. This paper proposes a general model for reconfigurable architectures and gives a set of metrics which prove useful for architecture characterization. These metrics are detailed and their interests is shown on several digital signal processing architectures. The methodology is then illustrated on a parametrable dynamically reconfigurable architecture: The Systolic Ring.