Scalable Security Mechanisms in Transport Systems for Enhanced Multimedia Services
ECMAST '98 Proceedings of the Third European Conference on Multimedia Applications, Services and Techniques
High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Using Second-Order Power Analysis to Attack DPA Resistant Software
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
ASIP design and synthesis for non linear filtering in image processing
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Efficient ASIP design for configurable processors with fine-grained resource sharing
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
An Unequal Secure Encryption Scheme for H.264/AVC Video Compression Standard
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
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Designing a hardware H.264 codec that meets the competing needs of the trusted battlefield communications is extremely challenging as it requires the evaluation of many potential architectural options to select an optimal solution. We discuss a solution to design a parameterized reconfigurable fabric that allows the architecture to be adjusted to meet the power, performance and security requirements.