ASIP design and synthesis for non linear filtering in image processing

Authors:
L. Fanucci;M. Cassiano;S. Saponara;D. Kammler;E. M. Witte;O. Schliebusch;G. Ascheid;R. Leupers;H. Meyr
Affiliations:
University of Pisa, Pisa, Italy;University of Pisa, Pisa, Italy;University of Pisa, Pisa, Italy;RWTH Aachen University, Templergraben, Aachen, Germany;RWTH Aachen University, Templergraben, Aachen, Germany;RWTH Aachen University, Templergraben, Aachen, Germany;RWTH Aachen University, Templergraben, Aachen, Germany;RWTH Aachen University, Templergraben, Aachen, Germany;RWTH Aachen University, Templergraben, Aachen, Germany
Venue:
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Year:
2006

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Abstract

This paper presents an Application Specific Instruction Set Processor (ASIP) design for the implementation of a class of nonlinear image processing algorithms, the Retinex-like filters. Starting from high level descriptions, first algorithmic optimization is accomplished. Then a processor architecture and an instruction set are customized with special respect to the algorithmic computations in order to achieve the specified timing at reasonable complexity. Taking advantage of the programmability of processor architectures, the flexibility of the system is increased, involving e.g. dynamic parameter adjustment and color treatment. ASIP implementation results in 0.13 μm CMOS technology are presented.