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Software—Practice & Experience - Special issue on discrete algorithm engineering
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
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ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
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FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
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FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
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FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
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VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
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FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
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FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
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IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
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ACM Transactions on Embedded Computing Systems (TECS)
EURASIP Journal on Applied Signal Processing
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A low-power CMOS thyristor based delay element with programmability extensions
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ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
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This article describes several multiplexer-based interconnection strategies designed to improve energy consumption of stripe-based coarse-grain reconfigurable fabrics. Application requirements for the architecture as well as two dense subgraphs are extracted from a suite of signal and image processing benchmarks. These statistics are used to drive the strategy of the composition of multiplexer-based interconnect. The article compares interconnects that are fully connected between stripes, those with a cardinality of 8:1 to 4:1, and extensions that provide a 5:1 cardinality, limited 6:1 cardinality, and hybrids between 5:1 and 3:1 cardinalities. Additionally, dedicated vertical routes are considered replacing some computational units with dedicated pass-gates. Using a fabric interconnect model (FIM) written in XML, we demonstrate that fabric instances and mappers can be automatically generated using a Web-based design flow. Upon testing these instances, we found that using an 8:1 cardinality interconnect with 33% of the computational units replaced with dedicated pass-gates provided the best energy versus mappability tradeoff, resulting in a 50% energy improvement over fully connected rows and 20% energy improvement over an 8:1 cardinality interconnect without dedicated vertical routes.