Evaluating register file size in ASIP design
Proceedings of the ninth international symposium on Hardware/software codesign
An efficient technique for exploring register file size in ASIP synthesis
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Methodical Low-Power ASIP Design Space Exploration
Journal of VLSI Signal Processing Systems
Exploring the Number of Register Windows in ASIP Synthesis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
SoC Synthesis with Automatic Hardware Software Interface Generation
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Designing a custom architecture for DCT using NISC technology
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An assertion-based verification methodology for system-level design
Computers and Electrical Engineering
ASIP Approach for Implementation of H.264/AVC
Journal of Signal Processing Systems
HyMacs: hybrid memory access optimization based on custom-instruction scheduling
Proceedings of the 18th ACM Great Lakes symposium on VLSI
C-based design flow: a case study on G.729A for voice over internet protocol (VoIP)
Proceedings of the 45th annual Design Automation Conference
Interconnect customization for a hardware fabric
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Embedded DSP Processor Design: Application Specific Instruction Set Processors
Embedded DSP Processor Design: Application Specific Instruction Set Processors
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Energy-performance Exploration of a CGA-based SDR Processor
Journal of Signal Processing Systems
A high performance heterogeneous architecture and its optimization design
HPCC'06 Proceedings of the Second international conference on High Performance Computing and Communications
A low-power globally synchronous locally asynchronous FFT processor
HPCC'07 Proceedings of the Third international conference on High Performance Computing and Communications
Proceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hybrid type legalization for a sparse SIMD instruction set
ACM Transactions on Architecture and Code Optimization (TACO)
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Interest in synthesis of Application Specific Instruction Processors or ASIPs has increased considerably and a number of methodologies have been proposed in the last decade. This paper attempts to survey the state of the art in this area and identifies some issues which need to be addressed. We have identified the five key steps in ASIP design as application analysis, architectural design space exploration, instruction set generation, code synthesis and hardware synthesis. A broad classification of the approaches reported in the literature is done. The paper notes the need to broaden the architectural space being explored and to tightly couple the various subtasks in ASIP synthesis.