Code scheduling and register allocation in large basic blocks
ICS '88 Proceedings of the 2nd international conference on Supercomputing
Register allocation over the program dependence graph
PLDI '94 Proceedings of the ACM SIGPLAN 1994 conference on Programming language design and implementation
Performance evaluation for application-specific architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An evaluation system for application specific architectures
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
Power efficient mediaprocessors: design space exploration
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Retargetable estimation scheme for DSP architecture selection
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Evaluating register file size in ASIP design
Proceedings of the ninth international symposium on Hardware/software codesign
URSA: A Unified ReSource Allocator for Registers and Functional Units in VLIW Architectures
PACT '93 Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism
Processor Evaluation in an Embedded Systems Design Environment
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
ASIP Design Methodologies: Survey and Issues
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Principles of Compiler Design (Addison-Wesley series in computer science and information processing)
Principles of Compiler Design (Addison-Wesley series in computer science and information processing)
Analysis of the influence of register file size on energy consumption, code size, and execution time
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic synthesis of system on chip multiprocessor architectures for process networks
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Journal of VLSI Signal Processing Systems
Register file partitioning and recompilation for register file power reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Performance estimation is a crucial operation which drives the design space exploration in Application Specific Instruction Set Processors (ASIP) synthesis. The usual approach to estimate performance is to do simulation. With increasing dimensions of the design space, simulator based approaches become too time consuming. This problem can be solved by scheduler based approaches, which are much faster. However existing scheduler based approaches do not help in exploring storage organization. This paper presents a scheduler based technique for exploring register file size in ASIP synthesis.The performance is estimated by estimating the number of spills for a particular register file size. The concept of register reuse chains is used for local register allocation. Live variable analysis is done across all the blocks to estimate global register needs. The technique is fast, accurate and retargetable and does not require code generation.Performance estimates for register file sizes between 1 to 8 for ARM (ARM7TDMI) and 1 to 128 for Trimedia (TM-1000) were generated for selected benchmarks to validate the proposed technique. Results show that our estimates are within 9.6% for ARM7T- DMI and 3.3% for TM-1000 compared to the actual performance produced by standard tool sets. Further, this technique is nearly 77 times faster compared to the simulator based technique encc.