Power analysis of embedded software: a first step towards software power minimization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A hardware/software partitioning algorithm for pipelined instruction set processor
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Synthesis of application specific instructions for embedded DSP software
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Retargetable estimation scheme for DSP architecture selection
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
An Integrated Design Environment for Application Specific Integrated Processor
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Processor Evaluation in an Embedded Systems Design Environment
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
ASIP Design Methodologies: Survey and Issues
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Application-Specific Pipelines for Exploiting Instruction-Level Parallelism
Application-Specific Pipelines for Exploiting Instruction-Level Parallelism
An efficient technique for exploring register file size in ASIP synthesis
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor
Proceedings of the conference on Design, automation and test in Europe - Volume 2
INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Dual-pipeline heterogeneous ASIP design
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Rapid Configuration and Instruction Selection for an ASIP: A Case Study
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Customization of application specific heterogeneous multi-pipeline processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
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Interest in synthesis of Application Specific Instruction Set Processors or ASIPs has increased considerably and a number of methodologies have been proposed for ASIP design. A key step in ASIP synthesis involves deciding architectural features based on application requirements and constraints. In this paper we observe the effect of changing register file size on the performance as well as power and energy consumption. Detailed data is generated and analyzed for a number of application programs. Results indicate that choice of an appropriate number of registers has a significant impact on performance.