EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
An ASIP instruction set optimization algorithm with functional module sharing constraint
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
MetaCore: an application specific DSP development system
DAC '98 Proceedings of the 35th annual Design Automation Conference
Instruction set selection for ASIP design
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Evaluating register file size in ASIP design
Proceedings of the ninth international symposium on Hardware/software codesign
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Instruction generation and regularity extraction for reconfigurable processors
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Instruction generation for hybrid reconfigurable systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Synthesis of custom processors based on extensible platforms
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Efficient instruction encoding for automatic instruction set design of configurable ASIPs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Processor Evaluation in an Embedded Systems Design Environment
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models
Proceedings of the conference on Design, automation and test in Europe
Rapid Configuration and Instruction Selection for an ASIP: A Case Study
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
Proceedings of the 41st annual Design Automation Conference
Satisfying real-time constraints with custom instructions
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Novel architecture for loop acceleration: a case study
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Battery-aware instruction generation for embedded processors
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 17th ACM Great Lakes symposium on VLSI
The Journal of Supercomputing
Speedups in embedded systems with a high-performance coprocessor datapath
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An efficient framework for dynamic reconfiguration of instruction-set customization
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
Evaluating design trade-offs in customizable processors
Proceedings of the 46th Annual Design Automation Conference
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
The Instruction-Set Extension Problem: A Survey
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Performance improvements of microprocessor platforms with a coarse-grained reconfigurable data-path
ICS'06 Proceedings of the 10th WSEAS international conference on Systems
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This paper presents the INSIDE system that rapidly searchesthe design space for extensible processors, given area and performance constraints of an embedded application, while minimizing the design turn-around-time. Our system consists ofa) a methodology to determine which code segments are mostsuited for implementation as a set of extensible instructions,b) a heuristic algorithm to select pre-configured extensibleprocessors as well as extensible instructions (library), and c)an estimation tool which rapidly estimates the performance ofan application on a generated extensible processor. By selecting the right combination of a processor core plus extensible instructions, we achieve a performance increase on average of 2.03x (up to 7x) compared to the base processor core at aminimum hardware overhead of 25% on average.