Evaluating register file size in ASIP design
Proceedings of the ninth international symposium on Hardware/software codesign
Scenario-based software characterization as a contingency to traditional program profiling
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
An efficient technique for exploring register file size in ASIP synthesis
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Compiler-directed customization of ASIP cores
Proceedings of the tenth international symposium on Hardware/software codesign
Architecture-level performance evaluation of component-based embedded systems
Proceedings of the 40th annual Design Automation Conference
Exploring the Number of Register Windows in ASIP Synthesis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Extending Platform-Based Design to Network on Chip Systems
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor
Proceedings of the conference on Design, automation and test in Europe - Volume 2
INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Rapid Configuration and Instruction Selection for an ASIP: A Case Study
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Microprocessors & Microsystems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
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In this paper, we present a novel methodology for processor evaluation in an embedded systems design environment. This evaluation can help in either selecting a suitable processor core or in evaluating changes to an ASIP. The processor evaluation is carried out in two stages. First, an architecture independent stage in which processors are rejected based on key application parameters and secondly, an architecture dependent stage in which performance is estimated on selected processors. The contribution of our work includes identification of application parameters which can influence processor selection, a mechanism to capture widely varying processor architectures and an instruction constrained scheduler. Initial experimental results suggest the potential of this approach.