FunState—an internal design representation for codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
System Design with SystemC
Code Optimization Techniques for Embedded Processors: Methods, Algorithms, and Tools
Code Optimization Techniques for Embedded Processors: Methods, Algorithms, and Tools
Processor Evaluation in an Embedded Systems Design Environment
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
System Design Using Kahn Process Networks: The Compaan/Laura Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Modular scheduling of guarded atomic actions
Proceedings of the 41st annual Design Automation Conference
A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels
IEEE Transactions on Computers
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Task-accurate performance modeling in SystemC for real-time multi-processor architectures
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Actor-oriented models for codesign: balancing re-use and performance
Formal methods and models for system design
UML-based multiprocessor SoC design framework
ACM Transactions on Embedded Computing Systems (TECS)
Hardware-Software Codesign of Multimedia Embedded Systems: the PeaCE
RTCSA '06 Proceedings of the 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Multi-processor system design with ESPAM
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Memory Management for Synthesis of DSP Software
Memory Management for Synthesis of DSP Software
A SystemC-based design methodology for digital signal processing systems
EURASIP Journal on Embedded Systems
Efficient design exploration based on module utility selection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Electronic system-level synthesis methodologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient high-level modeling in the networking domain
Proceedings of the Conference on Design, Automation and Test in Europe
Optimization of the bias current network for accurate on-chip thermal monitoring
Proceedings of the Conference on Design, Automation and Test in Europe
Analysis of SystemC actor networks for efficient synthesis
ACM Transactions on Embedded Computing Systems (TECS)
Application of ESL synthesis on GSM edge algorithm for base station
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Model-driven design-space exploration for embedded systems: the octopus toolset
ISoLA'10 Proceedings of the 4th international conference on Leveraging applications of formal methods, verification, and validation - Volume Part I
Microprocessors & Microsystems
A Model-Driven Design Framework for Massively Parallel Embedded Systems
ACM Transactions on Embedded Computing Systems (TECS)
A framework for high-level synthesis of heterogeneous MP-SoC
Proceedings of the great lakes symposium on VLSI
Hardware and software synthesis of heterogeneous systems from dataflow programs
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
Considering diagnosis functionality during automatic system-level design of automotive networks
Proceedings of the 49th Annual Design Automation Conference
Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Design space exploration towards a realtime and energy-aware GPGPU-based analysis of biosensor data
Computer Science - Research and Development
Mapping on multi/many-core systems: survey of current and emerging trends
Proceedings of the 50th Annual Design Automation Conference
CADSE: communication aware design space exploration for efficient run-time MPSoC management
Frontiers of Computer Science: Selected Publications from Chinese Universities
Proceedings of Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms
Design space exploration for high-level synthesis of multi-threaded applications
Journal of Systems Architecture: the EUROMICRO Journal
Solving system-level synthesis problem by a multi-objective estimation of distribution algorithm
Expert Systems with Applications: An International Journal
ASP-based optimized mapping in a simulink-to-MPSoC design flow
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Real-Time Image Processing
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With increasing design complexity, the gap from ESL (Electronic System Level) design to RTL synthesis becomes more and more crucial to many industrial projects. Although several behavioral synthesis tools exist to automatically generate synthesizable RTL code from C/C++/SystemC-based input descriptions and software generation for embedded processors is automated as well, an efficient ESL synthesis methodology combining both is still missing. This article presents SystemCoDesigner, a novel SystemC-based ESL tool to automatically optimize a hardware/software SoC (System on Chip) implementation with respect to several objectives. Starting from a SystemC behavioral model, SystemCoDesigner automatically extracts the mathematical model, performs a behavioral synthesis step, and explores the multiobjective design space using state-of-the-art multiobjective optimization algorithms. During design space exploration, a single design point is evaluated by simulating highly accurate performance models, which are automatically generated from the SystemC behavioral model and the behavioral synthesis results. Moreover, SystemCoDesigner permits the automatic generation of bit streams for FPGA targets from any previously optimized SoC implementation. Thus SystemCoDesigner is the first fully automated ESL synthesis tool providing a correct-by-construction generation of hardware/software SoC implementations. As a case study, a model of a Motion-JPEG decoder was automatically optimized and implemented using SystemCoDesigner. Several synthesized SoC variants based on this model show different tradeoffs between required hardware costs and achieved system throughput, ranging from software-only solutions to pure hardware implementations that reach real-time performance for QCIF streams on a 50MHz FPGA.