Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
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The future of multiprocessor systems-on-chips
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ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An optimal architecture for a DDC
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ACM Transactions on Embedded Computing Systems (TECS)
xTune: online verifiable cross-layer adaptation for distributed real-time embedded systems
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SystemCoDesigner: automatic design space exploration and rapid prototyping from behavioral models
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Design space exploration acceleration through operation clustering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Divide and conquer high-level synthesis design space exploration
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Microprocessors & Microsystems
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Real-time multi-media applications are increasingly being mapped onto MPSoC (multi-processor system-on-chip) platforms containing hardware-software IPs (intellectual property) along with a library of common scheduling policies such as EDF, RM. The choice of a scheduling policy for each IP is a key decision that greatly affects the design's ability to meet real-time constraints, and also directly affects the energy consumed by the design. We present a cosynthesis framework for design space exploration that considers heterogenous scheduling while mapping multimedia applications onto such MPSoCs. In our approach, we select a suitable scheduling policy for each IP such that system energy is minimized - our framework also includes energy reduction techniques utilizing dynamic power management. Experimental results on a realistic multi-mode multi-media terminal application demonstrate that our approach enables us to select design points with up to 60.5% reduced energy for a given area constraint, while meeting all real-time requirements. More importantly, our approach generates a tradeoff space between energy and cost allowing designers to comparatively evaluate multiple system level mappings.