Effective Platform-Level Exploration for Heterogeneous Multicores Exploiting Simulation-Induced Slacks

Authors:
Efstathios Sotiriou-Xanthopoulos;Sotirios Xydis;Kostas Siozios;George Economakos;Dimitrios Soudris
Affiliations:
School of Electrical and Computer Engineering, National Technical University of Athens (NTUA), Athens, Greece;School of Electrical and Computer Engineering, National Technical University of Athens (NTUA), Athens, Greece;School of Electrical and Computer Engineering, National Technical University of Athens (NTUA), Athens, Greece;School of Electrical and Computer Engineering, National Technical University of Athens (NTUA), Athens, Greece;School of Electrical and Computer Engineering, National Technical University of Athens (NTUA), Athens, Greece
Venue:
Proceedings of Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms
Year:
2014

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Abstract

Heterogeneous Multi-Processor Systems-on-Chip (MPSoC) exhibit increased design complexity due to numerous architectural parameters and hardware/software partitioning schemes. Automated Design Space Exploration (DSE) becomes an essential design procedure to discover optimized solutions in a reasonable time. For high-quality DSE, the accurate solution evaluation is a strong requirement. To this direction, High-Level Synthesis (HLS) can be used for the characterization of the design solutions. In this paper, we propose (a) a platform design methodology that exploits simulation-induced slacks generated by avoiding simulation re-initializations and exploits the gained time for HLS, and (b) a DSE tool-flow which takes into account multiple HW/SW partitioning schemes and intelligently schedules system evaluations. Experimental results show that the proposed methodology achieves 17% simulation improvements together with 77% higher accuracy, in comparison to a typical exploration approach.