Formal Models for Embedded System Design
IEEE Design & Test
System Design Using Kahn Process Networks: The Compaan/Laura Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware
Proceedings of the conference on Design, automation and test in Europe - Volume 3
LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
UML-based multiprocessor SoC design framework
ACM Transactions on Embedded Computing Systems (TECS)
PeaCE: A hardware-software codesign environment for multimedia embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A system for transforming an ANSI C code with OpenMP directives into a SystemC description
DDECS '06 Proceedings of the 2006 IEEE Design and Diagnostics of Electronic Circuits and systems
Daedalus: toward composable multimedia MP-SoC design
Proceedings of the 45th annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Compiler Design Using FLEX and YACC
Compiler Design Using FLEX and YACC
Electronic system-level synthesis methodologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
OpenMP extensions for FPGA accelerators
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
A new speculative addition architecture suitable for two's complement operations
Proceedings of the Conference on Design, Automation and Test in Europe
Early Prediction of Hardware Complexity in HLL-to-HDL Translation
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
An OpenMP Compiler for Efficient Use of Distributed Scratchpad Memory in MPSoCs
IEEE Transactions on Computers
Efficient and scalable OpenMP-based system-level design
Proceedings of the Conference on Design, Automation and Test in Europe
Fast Parallel GF(2^m) Polynomial Multiplication for All Degrees
IEEE Transactions on Computers
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We present an ESL methodology creating a direct path from high-level multi-threaded OpenMP applications to automatically synthesized, heterogeneous hardware/software systems implemented onto FPGA devices. The work addresses a number of challenges, including the definition of a novel system-oriented Model of Computation (MoC), capturing the essential aspects of the structure of a parallel software application related to the optimization and translation process, a key element to enable automated design space exploration. The paper also presents an analytical optimization model based on Integer Linear Programming, as well as innovative techniques for early hardware cost prediction used to speed up the design space exploration process. The methodology is supported by a set of ad hoc tools, including a custom OpenMP compiler and a hardware cost estimator, interacting with an existing ILP solver and a hardware high-level synthesis engine. The resulting prototypical environment demonstrates an innovative design flow that can extend the spectrum of ESL design to high-level multi-threaded applications, successfully meeting the current trends in complex embedded systems design. The work also presents a case-study to show the effectiveness of the proposed methodology with a real-world application.