The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
High-Radix Montgomery Modular Exponentiation on Reconfigurable Hardware
IEEE Transactions on Computers
Handbook of Applied Cryptography
Handbook of Applied Cryptography
Systolic Modular Multiplication
IEEE Transactions on Computers
Montgomery Modular Exponentiation on Reconfigurable Hardware
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
FPGA-Based Implementation of a Serial RSA Processor
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Novel Unified Architecture for Public-Key Cryptography
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
A new modular exponentiation architecture for efficient design of RSA cryptosystem
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient signed digit montgomery multiplication for RSA
Journal of Systems Architecture: the EUROMICRO Journal
A new algorithm for high-speed modular multiplication design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A direction to avoid re-encryption in cryptographic file sharing
NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing
High-Speed RSA crypto-processor with radix-4 modular multiplication and chinese remainder theorem
ICISC'06 Proceedings of the 9th international conference on Information Security and Cryptology
Design space exploration for high-level synthesis of multi-threaded applications
Journal of Systems Architecture: the EUROMICRO Journal
ASP-based optimized mapping in a simulink-to-MPSoC design flow
Journal of Systems Architecture: the EUROMICRO Journal
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In this paper we present a hardware implementation of the RSA algorithm for public-key cryptography. Basically, the RSA algorithm entails a modular exponentiation operation on large integers, which is considerably time-consuming to implement. To this end, we adopted a novelalgorithm combining the Montgomery's technique and the carry-save representation of numbers. A highly modular, bit-slice based architecture has been designed for executing the algorithm in hardware. We also propose an FPGA-based implementation of the architecture developed. The characteristics of the algorithm, the regularity of the architecture, and the data-flow aware placement of the FPGA resources resulted in a considerable performance improvement, as compared to other implementations presented in the literature.