High-Speed RSA crypto-processor with radix-4 modular multiplication and chinese remainder theorem

Authors:
Bonseok Koo;Dongwook Lee;Gwonho Ryu;Taejoo Chang;Sangjin Lee
Affiliations:
National Security Research Institute, Daejeon, Korea;National Security Research Institute, Daejeon, Korea;National Security Research Institute, Daejeon, Korea;National Security Research Institute, Daejeon, Korea;Graduate School of Information Security, Korea University, Seoul, Korea
Venue:
ICISC'06 Proceedings of the 9th international conference on Information Security and Cryptology
Year:
2006

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Abstract

Today, RSA is one of the most popular public-key crypto-system in various applications. In this paper, we present a high-speed RSA crypto-processor with modified radix-4 Montgomery multiplication algorithm and Chinese Remainder Theorem (CRT). Our design takes 0.84M clock cycles for a 1024-bit modular exponentiation and 0.25M clock cycles for two 512-bit exponentiations. Using 0.18 um standard cell library, the processor achieves 365Kbps for a 1024-bit exponentiation and 1,233Kbps for two 512-bit exponentiations at a 300MHz clock rate. For the high performance RSA crypto-system, the processor can also execute modular reduction, which is essential for calculating the Montgomery mapping constant and the modularly reduced ciphertext in CRT technique.