A new algorithm for high-speed modular multiplication design

Authors:
Ming-Der Shieh;Jun-Hong Chen;Wen-Ching Lin;Hao-Hsuan Wu
Affiliations:
Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan;Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan;Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan;Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Year:
2009

Citing 9
Cited 1

Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays

IEEE Transactions on Computers
Hardware Implementation of Montgomery's Modular Multiplication Algorithm

IEEE Transactions on Computers
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms

The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
A method for obtaining digital signatures and public-key cryptosystems

Communications of the ACM
Systolic Modular Multiplication

IEEE Transactions on Computers
A Scalable Architecture for Modular Multiplication Based on Montgomery's Algorithm

IEEE Transactions on Computers
Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware

Proceedings of the conference on Design, automation and test in Europe - Volume 3
An Improved Unified Scalable Radix-2 Montgomery Multiplier

ARITH '05 Proceedings of the 17th IEEE Symposium on Computer Arithmetic

Fast, compact and symmetric modular exponentiation architecture by common-multiplicand Montgomery modular multiplications

Integration, the VLSI Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

Modular exponentiation in public-key cryptosystems is usually achieved by repeated modular multiplications on large integers. Designing high-speed modular multiplication is thus very crucial to speed up the decryption/encryption process. In this paper, we first explore how to relax the data dependency that exists between multiplication, quotient determination, and modular reduction in the conventional Montgomery modular multiplication algorithm. Then, we propose a new modular multiplication algorithm for high-speed hardware design. The speed improvement is achieved by reducing the critical path delay from the 4-to-2 to 3-to-2 carry-save addition. The resulting time complexity of our development is further decreased by simultaneously performing the multiplication and modular reduction processes. Experimental results show that the developed modular multiplication can operate at speeds higher than those of related work. When the proposed modular multiplication is applied to modular exponentiation, both time and area-time advantages are obtained.