A common-multiplicand method to the Montgomery algorithm for speeding up exponentiation
Information Processing Letters
A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
High-Radix Montgomery Modular Exponentiation on Reconfigurable Hardware
IEEE Transactions on Computers
Area Efficient Exponentiation Using Modular Multiplier/Squarer in GF(2m
COCOON '01 Proceedings of the 7th Annual International Conference on Computing and Combinatorics
A Scalable Architecture for Montgomery Multiplication
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Implementation of RSA Algorithm Based on RNS Montgomery Multiplication
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
The Montgomery Powering Ladder
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Simplifying Quotient Determination in High-Radix Modular Multiplication
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
A Scalable Architecture for Modular Multiplication Based on Montgomery's Algorithm
IEEE Transactions on Computers
Information Sciences: an International Journal
A new algorithm for high-speed modular multiplication design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
New Hardware Architectures for Montgomery Modular Multiplication Algorithm
IEEE Transactions on Computers
CSA-based design of feedforward scalable montgomery modular multiplier
ISSPIT '11 Proceedings of the 2011 IEEE International Symposium on Signal Processing and Information Technology
New directions in cryptography
IEEE Transactions on Information Theory
A public key cryptosystem and a signature scheme based on discrete logarithms
IEEE Transactions on Information Theory
Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
In this paper, the primitive common-multiplicand Montgomery modular multiplication is developed for modular exponentiation. Together with Montgomery powering ladder, a fast, compact and symmetric modular exponentiation architecture is proposed for hardware implementation. The architecture consists of one group of processing elements along the central line and two symmetric groups of accumulation units on two sides. The central elements perform modular reductions, while the symmetric units on both sides accumulate the modular multiplication results. A feedforwarding architecture is employed to decrease the latency between processing elements, in parallel with the word-based accumulation units, which are also pipelined. Meanwhile, due to the symmetric architecture and Montgomery powering ladder, the modular exponentiation is immune from fault and simple power attacks. Implemented in FPGA platform, the performance of our proposed design outperforms most results so far in the literature.