Modulo Reduction in Residue Number Systems
IEEE Transactions on Parallel and Distributed Systems
Primality and Cryptography
Low-Cost Double-Size Modular Exponentiation or How to Stretch Your Cryptoprocessor
PKC '99 Proceedings of the Second International Workshop on Practice and Theory in Public Key Cryptography
An IWS Montgomery Modular Multiplication Algorithm
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
Cox-Rower architecture for fast parallel montgomery multiplication
EUROCRYPT'00 Proceedings of the 19th international conference on Theory and application of cryptographic techniques
Efficient Implementation of Elliptic Curve Cryptosystems on an ARM7 with Hardware Accelerator
ISC '01 Proceedings of the 4th International Conference on Information Security
How to Maximize the Potential of FPGA Resources for Modular Exponentiation
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Exploiting the Power of GPUs for Asymmetric Cryptography
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
A high speed coprocessor for elliptic curve scalar multiplications over Fp
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
Revisiting sum of residues modular multiplication
Journal of Electrical and Computer Engineering
FPGA implementation of pairings using residue number system and lazy reduction
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Area-time efficient end-around inverted carry adders
Integration, the VLSI Journal
The CRNS framework and its application to programmable and reconfigurable cryptography
ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers
Attacking RSA---CRT signatures with faults on montgomery multiplication
CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
Improving modular inversion in RNS using the plus-minus method
CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
| Hi-index | 0.00 |
We proposed a fast parallel algorithm of Montgomery multiplication based on Residue Number Systems (RNS). An implementation of RSA cryptosystem using the RNS Montgomery multiplication is described in this paper. We discuss how to choose the base size of RNS and the number of parallel processing units. An implementation method using the Chinese Remainder Theorem (CRT) is also presented. An LSI prototype adopting the proposed Cox-Rower Architecture achieves 1024- bit RSA transactions in 4.2 msec without CRT and 2.4 msec with CRT, when the operating frequency is 80 MHz and the total number of logic gates is 333 KG for 11 parallel processing units.