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CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
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CaLC '01 Revised Papers from the International Conference on Cryptography and Lattices
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IEEE Transactions on Computers
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Proceedings of the 17th ACM Great Lakes symposium on VLSI
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CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
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CT-RSA '09 Proceedings of the The Cryptographers' Track at the RSA Conference 2009 on Topics in Cryptology
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CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
PSS Is Secure against Random Fault Attacks
ASIACRYPT '09 Proceedings of the 15th International Conference on the Theory and Application of Cryptology and Information Security: Advances in Cryptology
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EUROCRYPT'97 Proceedings of the 16th annual international conference on Theory and application of cryptographic techniques
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ICISC'02 Proceedings of the 5th international conference on Information security and cryptology
An optimized hardware architecture for the montgomery multiplication algorithm
PKC'08 Proceedings of the Practice and theory in public key cryptography, 11th international conference on Public key cryptography
FDTC '10 Proceedings of the 2010 Workshop on Fault Diagnosis and Tolerance in Cryptography
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FDTC '10 Proceedings of the 2010 Workshop on Fault Diagnosis and Tolerance in Cryptography
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FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
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CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
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EUROCRYPT'12 Proceedings of the 31st Annual international conference on Theory and Applications of Cryptographic Techniques
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In this paper, we present several efficient fault attacks against implementations of RSA---CRT signatures that use modular exponentiation algorithms based on Montgomery multiplication. They apply to any padding function, including randomized paddings, and as such are the first fault attacks effective against RSA---PSS. The new attacks work provided that a small register can be forced to either zero, or a constant value, or a value with zero high-order bits. We show that these models are quite realistic, as such faults can be achieved against many proposed hardware designs for RSA signatures.