Efficient pipelining for modular multiplication architectures in prime fields

  • Authors:
  • Nele Mentens;Kazuo Sakiyama;Bart Preneel;Ingrid Verbauwhede

  • Affiliations:
  • Katholieke Universiteit Leuven, Heverlee (Leuven), Belgium;Katholieke Universiteit Leuven, Heverlee (Leuven), Belgium;Katholieke Universiteit Leuven, Heverlee (Leuven), Belgium;Katholieke Universiteit Leuven, Heverlee (Leuven), Belgium

  • Venue:
  • Proceedings of the 17th ACM Great Lakes symposium on VLSI
  • Year:
  • 2007

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Abstract

This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation of the Montgomery algorithm, a more compact pipelined version is derived. The design makes use of 16-bit integer multiplication blocks that are available on recently manufactured FPGAs. The critical path is optimized by omitting the exact computation of intermediate results in the Montgomery algorithm using a 6-2 carry-save notation. This results in a high-speed architecture,which outperforms previously designed Montgomery multipliers. Because a very popular application of Montgomery multiplication is public key cryptography, we compare our implementation to the state-of-the-art in Montgomery multipliers on the basis of performance results for 1024-bit RSA.