Hardware Implementation of Montgomery's Modular Multiplication Algorithm
IEEE Transactions on Computers
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
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IEEE Transactions on Computers
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IEEE Transactions on Computers
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CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
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CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
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CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
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CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
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IEEE Transactions on Computers
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ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
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ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
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FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
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CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
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ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
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CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
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CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
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CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
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This paper describes a modular exponentiation processing method and circuit architecture that can exhibit the maximum performance of FPGA resources. The modular exponentiation architecture proposed by us comprises three main techniques. The first technique is to improve the Montgomery multiplication algorithm in order to maximize the performance of the multiplication unit in FPGA. The second technique is to improve and balance the circuit delay. The third technique is to ensure and make fast the scalability of the effective FPGA resource. We propose a circuit architecture that can handle multiple data lengths using the same circuits. In addition, our architecture can perform fast operations using small-scale resources; in particular, it can complete 512-bit modular exponentiation in 0.26 ms by means of XC4VF12-10SF363, which is the minimum logic resources in the Virtex-4 Series FPGAs. Also, the number of SLICEs used is approx. 4000 to make a very compact design. Moreover, 1024-, 1536- and 2048-bit modular exponentiations can be processed in the same circuit with the scalability.