High-Radix Montgomery Modular Exponentiation on Reconfigurable Hardware
IEEE Transactions on Computers
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
How to Maximize the Potential of FPGA Resources for Modular Exponentiation
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Parametric, Secure and Compact Implementation of RSA on FPGA
RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
Constructing cluster of simple FPGA boards for cryptologic computations
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
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We present new scalable hardware designs of modular multiplication, modular exponentiation and primality test. These operations are at the core of most public-key crypto-systems. All the modules are based on an original Montgomery modular multiplier. Our multiplier is the first Montgomery multiplier design with variable pipeline stages and variable serial replications. It is 8 times faster than the best existing hardware implementation and 30 times faster than an optimised software implementation on an Intel Core 2 Duo running at 2.8 GHz. Our exponentiator is 2.4 times faster than an optimised software implementation. It reaches the performance of a more complex FPGA design using DSP blocks which is the fastest in the literature. Our prime tester is 2.2 times faster than the software implementation and is 85 times faster than hardware implementations of the same algorithm with only 60% area overhead.