Cracking DES: Secrets of Encryption Research, Wiretap Politics and Chip Design
Cracking DES: Secrets of Encryption Research, Wiretap Politics and Chip Design
Optimisation of the SHA-2 Family of Hash Functions on FPGAs
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
How to Maximize the Potential of FPGA Resources for Modular Exponentiation
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
CAIRN 2: An FPGA Implementation of the Sieving Step in the Number Field Sieve Method
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
E-Passport: cracking basic access control keys
OTM'07 Proceedings of the 2007 OTM confederated international conference on On the move to meaningful internet systems: CoopIS, DOA, ODBASE, GADA, and IS - Volume Part II
Breaking ciphers with COPACOBANA –a cost-optimized parallel code breaker
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Improving SHA-2 hardware implementations
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
How far can we go on the x64 processors?
FSE'06 Proceedings of the 13th international conference on Fast Software Encryption
Linguistic properties of multi-word passphrases
FC'12 Proceedings of the 16th international conference on Financial Cryptography and Data Security
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We propose a high-speed passphrase-search system for PGP using FPGA for the purpose of evaluating PGP's passphrase-based security. In order to implement a high-speed search circuit on a single FPGA, we manage to surmount three major hurdles in PGP. The first one, multiprecision arithmetics which arises a problem of speed, is cleared by reducing the number of arithmetics needed. The second one, heavy iteration of hashing which also lowers the search speed, is settled by pipelining the hash function. The last one, candidate passphrase generation which cannot be implemented on hardware, is treated by combining a PC with the FPGA. We thereby achieve a throughput of 56 Gbps per FPGA that amounts to 1.1 ×105 passphrases per second. Compared with a fully software-based search, it shows 38 times faster the speed. We also propose to use an embedded FPGA system and to have part of software such as passphrase generation, to be run on a CPU inside the FPGA. We expect the search system to be more self-contained in an FPGA and thus to have a lower risk of data bus bottleneck between PCs and FPGAs especially in a massive parallel system where many FPGAs are connected to one PC.