Design Methodology for Throughput Optimum Architectures of Hash Algorithms of the MD4-class
Journal of Signal Processing Systems
High-Speed Search System for PGP Passphrases
CANS '08 Proceedings of the 7th International Conference on Cryptology and Network Security
Cost-efficient SHA hardware accelerators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Hardware Architecture for Integrated-Security Services
Transactions on Computational Science IV
Efficient Hardware Architecture of SHA-256 Algorithm for Trusted Mobile Computing
Information Security and Cryptology
WISA'07 Proceedings of the 8th international conference on Information security applications
Improving SHA-2 hardware implementations
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
On the exploitation of a high-throughput SHA-256 FPGA design for HMAC
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
On the exploitation of a high-throughput SHA-256 FPGA design for HMAC
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Securely sealing Multi-FPGA systems
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Hardware performance optimization and evaluation of SM3 hash algorithm on FPGA
ICICS'12 Proceedings of the 14th international conference on Information and Communications Security
Secure event logging in sensor networks
Computers & Mathematics with Applications
FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256
Microprocessors & Microsystems
Compact and unified hardware architecture for SHA-1 and SHA-256 of trusted mobile computing
Personal and Ubiquitous Computing
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Hash functions play an important role in modern cryptography. This paper investigates optimisation techniques that have recently been proposed in the literature. A new VLSI architecture for the SHA-256 and SHA-512 hash functions is presented, which combines two popular hardware optimisation techniques, namely pipelining and unrolling. The SHA processors are developed for implementation on FPGAs, thereby allowing rapid prototyping of several designs. Speed/area results from these processors are analysed and are shown to compare favourably with other FPGA-based implementations, achieving the fastest data throughputs in the literature to date.