The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512)
Proceedings of the conference on Design, automation and test in Europe - Volume 3
An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512)
Proceedings of the 14th ACM Great Lakes symposium on VLSI
ASIC-Hardware-Focused Comparison for Hash Functions MD5, RIPEMD-160, and SHS
ITCC '05 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'05) - Volume I - Volume 01
ITCC '05 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'05) - Volume I - Volume 01
ARITH '05 Proceedings of the 17th IEEE Symposium on Computer Arithmetic
Optimisation of the SHA-2 Family of Hash Functions on FPGAs
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Design Methodology for Throughput Optimum Architectures of Hash Algorithms of the MD4-class
Journal of Signal Processing Systems
Hardware evaluation of the Luffa hash family
WESS '09 Proceedings of the 4th Workshop on Embedded Systems Security
Hardware evaluation of the stream cipher-based hash functions RadioGatún and irRUPT
Proceedings of the Conference on Design, Automation and Test in Europe
Architectural support for hypervisor-secure virtualization
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
A compact FPGA-based processor for the Secure Hash Algorithm SHA-256
Computers and Electrical Engineering
Hi-index | 0.00 |
The hash algorithm forms the basis of many popular cryptographic protocols and it is therefore important to find throughput optimal implementations. Though there have been numerous published papers proposing high throughput architectures, none of them have claimed to be optimal. In this paper, we perform iteration bound analysis on the SHA2 family of hash algorithms. Using this technique, we are able to both calculate the theoretical maximum throughput and determine the architecture that achieves this throughput. In addition to providing the throughput optimal architecture for SHA2, the techniques presented can also be used to analyze and design optimal architectures for some other iterative hash algorithms.