An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512)
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Throughput Optimized SHA-1 Architecture Using Unfolding Transformation
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
ASIC-hardware-focused comparison for hash functions MD5, RIPEMD-160, and SHS
Integration, the VLSI Journal - Special issue: Embedded cryptographic hardware
WISA'07 Proceedings of the 8th international conference on Information security applications
Power efficient hardware architecture of SHA-1 algorithm for trusted mobile computing
ICICS'07 Proceedings of the 9th international conference on Information and communications security
Finding collisions in the full SHA-1
CRYPTO'05 Proceedings of the 25th annual international conference on Advances in Cryptology
How to break MD5 and other hash functions
EUROCRYPT'05 Proceedings of the 24th annual international conference on Theory and Applications of Cryptographic Techniques
Proceedings of the 3rd international conference on Security of information and networks
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Efficient hardware architectures for the Luffa hash algorithm are proposed in this work. We explore different tradeoffs and propose several architectures, targeting both compact and high-throughput designs. Implemented using UMC 0.13 μm CMOS standard cell library, the most compact architecture of Luffa-224/256 contains 18,260 GE. The same version, optimized for speed, achieves a throughput of almost 32 Gbps, while the throughput of the pipelined design approaches 291.7 Gbps. Concerning the final throughput, our implementations outperform state of the art implementations of the existing hash standards.