The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512)

Authors:
Luigi Dadda;Marco Macchetti;Jeff Owen
Affiliations:
-;-;-
Venue:
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Year:
2004

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Abstract

After recalling the basic algorithms published by NIST for implementing the hash functions SHA-256 (384, 512), a basic circuit characterized by a cascade of full adder arrays is given. Implementation options are discussed and two methods for improving speed are exposed: the delay balancing and the pipelining. An application of the former is first given, obtaining a circuit that reduces the length of the critical path by a full adder array. A pipelined version is then given, obtaining a reduction of two full adder arrays in the critical path. The two methods are afterwards combined and the results obtained through hardware synthesis are exposed, where a comparison between the new circuits is also given.