The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512)
Proceedings of the conference on Design, automation and test in Europe - Volume 3
An HMAC processor with integrated SHA-1 and MD5 algorithms
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
ARITH '05 Proceedings of the 17th IEEE Symposium on Computer Arithmetic
Hashchip: a shared-resource multi-hash function processor architecture on FPGA
Integration, the VLSI Journal - Special issue: Embedded cryptographic hardware
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
XBX: eXternal benchmarking eXtension for the SUPERCOP crypto benchmarking framework
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
RECONFIG '10 Proceedings of the 2010 International Conference on Reconfigurable Computing and FPGAs
On FPGA-Based Implementations of the SHA-3 Candidate Grøstl
RECONFIG '10 Proceedings of the 2010 International Conference on Reconfigurable Computing and FPGAs
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Efficient Hardware Accelerator for IPSec Based on Partial Reconfiguration on Xilinx FPGAs
RECONFIG '11 Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs
A High-Speed Unified Hardware Architecture for AES and the SHA-3 Candidate Grøstl
DSD '12 Proceedings of the 2012 15th Euromicro Conference on Digital System Design
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One of the five final SHA-3 candidates, Grostl, has been inspired by the Advanced Encryption Standard. This unique feature can be exploited in a large variety of practical applications. In order to have a better picture of the Grostl-AES computational efficiency (high-level scheduling, internal pipelining, resource sharing, etc.), we designed a high-speed coprocessor for the Grostl-based HMAC and AES in the counter mode. This coprocessor offers high-speed computations of both authentication and encryption/decryption with relatively small penalty in terms of area and speed when compared to the authentication (original Grostl circuitry) functionality only. From our perspective, the main advantage of Grostl over other finalists is the fact that its hardware architecture naturally accommodates AES at the cost of a small area overhead.