Fair and comprehensive methodology for comparing hardware performance of fourteen round two SHA-3 candidates using FPGAs

Authors:
Kris Gaj;Ekawat Homsirikamol;Marcin Rogawski
Affiliations:
ECE Department, George Mason University, Fairfax, VA;ECE Department, George Mason University, Fairfax, VA;ECE Department, George Mason University, Fairfax, VA
Venue:
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
Year:
2010

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Abstract

Performance in hardware has been demonstrated to be an important factor in the evaluation of candidates for cryptographic standards. Up to now, no consensus exists on how such an evaluation should be performed in order to make it fair, transparent, practical, and acceptable for the majority of the cryptographic community. In this paper, we formulate a proposal for a fair and comprehensive evaluation methodology, and apply it to the comparison of hardware performance of 14 Round 2 SHA-3 candidates. The most important aspects of our methodology include the definition of clear performance metrics, the development of a uniform and practical interface, generation of multiple sets of results for several representative FPGA families from two major vendors, and the application of a simple procedure to convert multiple sets of results into a single ranking.