Fair and consistent hardware evaluation of fourteen round two SHA-3 candidates

Authors:
Miroslav Knežević;Kazuyuki Kobayashi;Jun Ikegami;Shin'ichiro Matsuo;Akashi Satoh;Ünal Kocabaş;Junfeng Fan;Toshihiro Katashita;Takeshi Sugawara;Kazuo Sakiyama;Ingrid Verbauwhede;Kazuo Ohta;Naofumi Homma;Takafumi Aoki
Affiliations:
Katholieke Universiteit Leuven, ESAT, SCD-COSIC and IBBT, Leuven-Heverlee, Belgium;The University of Electro-Communications, Chofu, Tokyo, Japan;The University of Electro-Communications, Chofu, Tokyo, Japan;National Institute of Information and Communications Technology, Koganei, Tokyo, Japan;Research Center for Information Security, National Institute of Advanced Industrial Science and Technology, Tokyo, Japan;Katholieke Universiteit Leuven, ESAT, SCD-COSIC and IBBT, Leuven-Heverlee, Belgium;Katholieke Universiteit Leuven, ESAT, SCD-COSIC and IBBT, Leuven-Heverlee, Belgium;Research Center for Information Security, National Institute of Advanced Industrial Science and Technology, Tokyo, Japan;Graduate School of Information Sciences, Tohoku University, Sendai, Japan;The University of Electro-Communications, Chofu, Tokyo, Japan;Katholieke Universiteit Leuven, ESAT, SCD-COSIC and IBBT, Leuven-Heverlee, Belgium;The University of Electro-Communications, Chofu, Tokyo, Japan;Graduate School of Information Sciences, Tohoku University, Sendai, Japan;Graduate School of Information Sciences, Tohoku University, Sendai, Japan
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2012

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Abstract

The first contribution of our paper is that we propose a platform, a design strategy, and evaluation criteria for a fair and consistent hardware evaluation of the second-round SHA-3 candidates. Using a SASEBO-GII field-programmable gate array (FPGA) board as a common platform, combined with well defined hardware and software interfaces, we compare all 256-bit version candidates with respect to area, throughput, latency, power, and energy consumption. Our approach defines a standard testing harness for SHA-3 candidates, including the interface specification for the SHA-3 module on our testing platform. The second contribution is that we provide both FPGA and 90-nm CMOS application-specific integrated circuit (ASIC) synthesis results and thereby are able to compare the results. Our third contribution is that we release the source code of all the candidates and by using a common, fixed, publicly available platform, our claimed results become reproducible and open for a public verification.