SPONGENT: a lightweight hash function
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
SPN-hash: improving the provable resistance against differential collision attacks
AFRICACRYPT'12 Proceedings of the 5th international conference on Cryptology in Africa
Design and benchmarking of an ASIC with five SHA-3 finalist candidates
Microprocessors & Microsystems
CoARX: a coprocessor for ARX-based cryptographic algorithms
Proceedings of the 50th Annual Design Automation Conference
Fair and consistent hardware evaluation of fourteen round two SHA-3 candidates
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ASIC implementations of five SHA-3 finalists
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Cryptographic hash functions are used to protect information integrity and authenticity in a wide range of applications. After the discovery of weaknesses in the current deployed standards, the U.S. Institute of Standards and Technology started a public competition to develop the future standard SHA-3, which will be implemented in a multitude of environments, after its selection in 2012. In this paper, we investigate high-speed and low-area hardware architectures of one of the 14 “second-round” candidates in this competition: BLAKE. VLSI performance results of the proposed high-speed designs indicate a throughput improvement between 16% and 36% compared to the current standard SHA-2. Additionally, we propose a compact implementation of BLAKE with memory optimization that fits in 0.127 mm2 of a 0.18 μ m CMOS. Measurements reveal a minimal power dissipation of 9.59 μW/MHz at 0.65 V, which suggests that BLAKE is suitable for resource-limited systems.