Developing a hardware evaluation method for SHA-3 candidates
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
Pre-silicon Characterization of NIST SHA-3 Final Round Candidates
DSD '11 Proceedings of the 2011 14th Euromicro Conference on Digital System Design
VLSI Characterization of the Cryptographic Hash Function BLAKE
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CoARX: a coprocessor for ARX-based cryptographic algorithms
Proceedings of the 50th Annual Design Automation Conference
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Throughout the NIST SHA-3 competition, in relative order of importance, NIST considered the security, cost, and algorithm and implementation characteristics of a candidate [1]. Within the limited one-year security evaluation period for the five SHA-3 finalists, the cost and performance evaluation may put more weight in the selection of winner. This work contributes to the SHA-3 hardware evaluation by providing timely cost and performance results on the first SHA-3 ASIC in 0.13 μm IBM process using standard cell CMOS technology with measurements of all the five finalists using the latest Round 3 tweaks. This article describes the SHA-3 ASIC design from VLSI architecture implementation to the silicon realization.