Design Methodology for Throughput Optimum Architectures of Hash Algorithms of the MD4-class
Journal of Signal Processing Systems
Cost-efficient SHA hardware accelerators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
WISA'07 Proceedings of the 8th international conference on Information security applications
A Fault Detection Scheme for the FPGA Implementation of SHA-1 and SHA-512 Round Computations
Journal of Electronic Testing: Theory and Applications
Improving SHA-2 hardware implementations
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Hardware performance optimization and evaluation of SM3 hash algorithm on FPGA
ICICS'12 Proceedings of the 14th international conference on Information and Communications Security
Microprocessors & Microsystems
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Recent research has demonstrated the vulnerability of certain smart card architectures to power and electro-magnetic analysis when multiplier operations areinsufficiently shielded from external monitoring. Here several standard multipliers are investigated ...