Comparative Analysis of the Hardware Implementations of Hash Functions SHA-1 and SHA-512
ISC '02 Proceedings of the 5th International Conference on Information Security
The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512)
Proceedings of the conference on Design, automation and test in Europe - Volume 3
An Efficient Hardware-Based Fault Diagnosis Scheme for AES: Performances and Cost
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
ARITH '05 Proceedings of the 17th IEEE Symposium on Computer Arithmetic
Low Cost Concurrent Error Detection for the Advanced Encryption Standard
ITC '04 Proceedings of the International Test Conference on International Test Conference
Simple Error Detection Methods for Hardware Implementation of Advanced Encryption Standard
IEEE Transactions on Computers
Analysis and Detection Of Errors In Implementation Of SHA-512 Algorithms On FPGAs
The Computer Journal
High-Performance Concurrent Error Detection Scheme for AES Hardware
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Cost-efficient SHA hardware accelerators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The Secure Hash Algorithm is the most popular hash function currently used in many security protocols such as SSL and IPSec. Like other cryptographic algorithms, the hardware implementation of hash functions is of great importance for high speed applications. Because of the iterative structure of hash functions, a single error in their hardware implementation could result in a large number of errors in the final hash value. In this paper, we propose a novel time-redundancy-based fault diagnostic scheme for the implementation of SHA-1 and SHA-512 round computations. This scheme can detect permanent as well as transient faults as opposed to the traditional time redundancy technique which is only capable of detecting transient errors. The proposed design does not impose significant timing overhead to the original implementation of SHA-1 and SHA-512 round computation. We have implemented the proposed design for SHA-1 and SHA-512 on Xilinx xc2p7 FPGA. It is shown that for the proposed fault detection SHA-1 and SHA-512 round computations, there are, respectively, 3% and 10% reduction in the throughput with 58% and 30% area overhead as compared to the original schemes. The fault simulation of the implementation shows that almost 100% fault coverage can be achieved using the proposed scheme for transient and permanent faults.