An Efficient Hardware-Based Fault Diagnosis Scheme for AES: Performances and Cost

Authors:
Guido Bertoni;Luca Breveglieri;Israel Koren;Paolo Maistri
Affiliations:
STMicroelectronics, Milano, Italy;Politecnico di Milano, Italy;University of Massachusetts, Amherst;Politecnico di Milano, Italy
Venue:
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Year:
2004

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Abstract

Since standardization in 2001, the Advanced Encryption Standard has been the subject of many research efforts, aimed at developing effcient hardware implementations with reduced area and latency. So far, reliability has not been considered a primary objective. Recently, several error detecting schemes have been proposed in order to provide some defenseagainst hardware faults in AES. The benefits of such schemes are twofold: avoiding wrong outputs when benign hardware faults occur, and preventing the collection of informationabout the secret key through malicious injection of faults. In this paper, we present a complete scheme for parity-based fault detection in a hardware implementation of the Advanced Encryption Standard which includes a key schedule unit. We also provide a preliminary evaluation of the hardware and latency overhead of the proposed scheme.