An ASIC Implementation of the AES SBoxes
CT-RSA '02 Proceedings of the The Cryptographer's Track at the RSA Conference on Topics in Cryptology
A Compact Rijndael Hardware Architecture with S-Box Optimization
ASIACRYPT '01 Proceedings of the 7th International Conference on the Theory and Application of Cryptology and Information Security: Advances in Cryptology
Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
An Optimized S-Box Circuit Architecture for Low Power AES Design
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
A Highly Regular and Scalable AES Hardware Architecture
IEEE Transactions on Computers
IEEE Transactions on Computers
Carry checking/parity prediction adders and ALUs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
An Efficient Hardware-Based Fault Diagnosis Scheme for AES: Performances and Cost
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
High-speed VLSI architectures for the AES algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
A Self Checking Reed Solomon Encoder: Design and Analysis
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors
IEEE Transactions on Computers
Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders
IEEE Transactions on Computers
Simple Error Detection Methods for Hardware Implementation of Advanced Encryption Standard
IEEE Transactions on Computers
Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic
IEEE Transactions on Computers
Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
A systematic evaluation of compact hardware implementations for the rijndael s-box
CT-RSA'05 Proceedings of the 2005 international conference on Topics in Cryptology
Successfully attacking masked AES hardware implementations
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A compact AES core with on-line error-detection for FPGA applications with modest hardware resources
Microprocessors & Microsystems
Meet-in-the-middle and impossible differential fault analysis on AES
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
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The use of an appropriate fault detection scheme for hardware implementation of the Advanced Encryption Standard (AES) makes the standard robust to the internal defects and fault attacks. To minimize the overhead cost of the fault detection AES structure, we present a lightweight concurrent fault detection scheme for the composite field realization of the S-box using normal basis. The structure of the S-box is divided into blocks and the predicted parities of these blocks are obtained. Through an exhaustive search among all available composite fields and transformation matrices that map the polynomial basis representation in binary field to the normal basis representation in composite field, we have found the optimum solution for the least overhead S-box and its parity predictions. Finally, using FPGA implementations, the complexities of the proposed schemes are compared to those of the previously reported ones. It is shown that the FPGA implementations of the S-box using normal basis representation in composite fields outperform the traditional ones using polynomial basis for both with and without fault detection capability.