IEEE Transactions on Computers
Efficient Algorithms for Elliptic Curve Cryptosystems
CRYPTO '97 Proceedings of the 17th Annual International Cryptology Conference on Advances in Cryptology
Design Methodology for a One-Shot Reed-Solomon Encoder and Decoder
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Security of a Wide Trail Design
INDOCRYPT '02 Proceedings of the Third International Conference on Cryptology: Progress in Cryptology
An Optimized S-Box Circuit Architecture for Low Power AES Design
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
A High Performance Sub-Pipelined Architecture for AES
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
On the implementation of the advanced encryption standard on a public-key crypto-coprocessor
CARDIS'02 Proceedings of the 5th conference on Smart Card Research and Advanced Application Conference - Volume 5
On the Power of Bitslice Implementation on Intel Core2 Processor
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
AES Encryption Implementation and Analysis on Commodity Graphics Processing Units
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
New Stream Cipher Designs
High-Performance Concurrent Error Detection Scheme for AES Hardware
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
A Lightweight Concurrent Fault Detection Scheme for the AES S-Boxes Using Normal Basis
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Ultra-Lightweight Implementations for Smart Devices --- Security for 1000 Gate Equivalents
CARDIS '08 Proceedings of the 8th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
A Practical DPA Countermeasure with BDD Architecture
CARDIS '08 Proceedings of the 8th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
Vortex: A New Family of One-Way Hash Functions Based on AES Rounds and Carry-Less Multiplication
ISC '08 Proceedings of the 11th international conference on Information Security
Using Normal Bases for Compact Hardware Implementations of the AES S-Box
SCN '08 Proceedings of the 6th international conference on Security and Cryptography for Networks
A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
International Journal of High Performance Systems Architecture
Proceedings of the ACM SIGCOMM 2010 conference
Correlation-enhanced power analysis collision attack
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
Mixed bases for efficient inversion in F((22)2)2 and conversion matrices of SubBytes of AES
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
692-nW advanced encryption standard (AES) on a 0.13-µm CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On side-channel resistant block cipher usage
ISC'10 Proceedings of the 13th international conference on Information security
Inv mix column decomposition and multilevel resource sharing in AES implementations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cryptanalysis of CLEFIA using differential methods with cache trace patterns
CT-RSA'11 Proceedings of the 11th international conference on Topics in cryptology: CT-RSA 2011
Implementation of AES algorithm on ARM
Proceedings of the International Conference & Workshop on Emerging Trends in Technology
FastCrypto: parallel AES pipelines extension for general-purpose processors
Neural, Parallel & Scientific Computations
AES variants secure against related-key differential and boomerang attacks
WISTP'11 Proceedings of the 5th IFIP WG 11.2 international conference on Information security theory and practice: security and privacy of mobile devices in wireless communication
A fast and provably secure higher-order masking of AES S-box
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Design of an ultra high speed AES processor for next generation IT security
Computers and Electrical Engineering
Provably secure masking of AES
SAC'04 Proceedings of the 11th international conference on Selected Areas in Cryptography
A side-channel analysis resistant description of the AES s-box
FSE'05 Proceedings of the 12th international conference on Fast Software Encryption
Pinpointing the side-channel leakage of masked AES hardware implementations
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
NanoCMOS-molecular realization of rijndael
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
How far can we go on the x64 processors?
FSE'06 Proceedings of the 13th international conference on Fast Software Encryption
A new combinational logic minimization technique with applications to cryptology
SEA'10 Proceedings of the 9th international conference on Experimental Algorithms
DPA-resistant finite field multipliers and secure AES design
ISPEC'06 Proceedings of the Second international conference on Information Security Practice and Experience
A systematic evaluation of compact hardware implementations for the rijndael s-box
CT-RSA'05 Proceedings of the 2005 international conference on Topics in Cryptology
Side-channel leakage of masked CMOS gates
CT-RSA'05 Proceedings of the 2005 international conference on Topics in Cryptology
Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Efficient AES implementations on ASICs and FPGAs
AES'04 Proceedings of the 4th international conference on Advanced Encryption Standard
Small size, low power, side channel-immune AES coprocessor: design and synthesis results
AES'04 Proceedings of the 4th international conference on Advanced Encryption Standard
Representations and rijndael descriptions
AES'04 Proceedings of the 4th international conference on Advanced Encryption Standard
AES on FPGA from the fastest to the smallest
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Secure AES hardware module for resource constrained devices
ESAS'04 Proceedings of the First European conference on Security in Ad-hoc and Sensor Networks
Area, delay, and power characteristics of standard-cell implementations of the AES s-box
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Low power AES hardware architecture for radio frequency identification
IWSEC'06 Proceedings of the 1st international conference on Security
The smallest ARIA module with 16-bit architecture
ICISC'06 Proceedings of the 9th international conference on Information Security and Cryptology
A first-order leak-free masking countermeasure
CT-RSA'12 Proceedings of the 12th conference on Topics in Cryptology
A new difference method for side-channel analysis with high-dimensional leakage models
CT-RSA'12 Proceedings of the 12th conference on Topics in Cryptology
KLEIN: a new family of lightweight block ciphers
RFIDSec'11 Proceedings of the 7th international conference on RFID Security and Privacy
RFIDSec'11 Proceedings of the 7th international conference on RFID Security and Privacy
Secure and fast implementations of two involution ciphers
NordSec'10 Proceedings of the 15th Nordic conference on Information Security Technology for Applications
Optimal first-order masking with linear and non-linear bijections
AFRICACRYPT'12 Proceedings of the 5th international conference on Cryptology in Africa
LRCG: latch-based random clock-gating for preventing power analysis side-channel attacks
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Correlation power analysis attack of AES on FPGA using customized communication protocol
Proceedings of the Second International Conference on Computational Science, Engineering and Information Technology
FSE'07 Proceedings of the 14th international conference on Fast Software Encryption
High-speed pipelined hardware architecture for Galois counter mode
ISC'07 Proceedings of the 10th international conference on Information Security
Higher-Order masking schemes for s-boxes
FSE'12 Proceedings of the 19th international conference on Fast Software Encryption
Secure event logging in sensor networks
Computers & Mathematics with Applications
On the use of shamir's secret sharing against side-channel analysis
CARDIS'12 Proceedings of the 11th international conference on Smart Card Research and Advanced Applications
Construction of optimum composite field architecture for compact high-throughput AES S-boxes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Selective secure error correction on SPIHT coefficients for pervasive wireless visual network
International Journal of Ad Hoc and Ubiquitous Computing
Low-power compact composite field AES S-Box/Inv S-Box design in 65nm CMOS using Novel XOR Gate
Integration, the VLSI Journal
Chosen-IV correlation power analysis on KCipher-2 and a countermeasure
COSADE'13 Proceedings of the 4th international conference on Constructive Side-Channel Analysis and Secure Design
Cancellation-Free circuits in unbounded and bounded depth
FCT'13 Proceedings of the 19th international conference on Fundamentals of Computation Theory
Analysis and improvement of the generic higher-order masking scheme of FSE 2012
CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
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Compact and high-speed hardware architectures and logic optimization methods for the AES algorithm Rijndael are described. Encryption and decryption data paths are combined and all arithmetic components are reused. By introducing a new composite field, the S-Box structure is also optimized. An extremely small size of 5.4 Kgates is obtained for a 128-bit key Rijndael circuit using a 0.11-µm CMOS standard cell library. It requires only 0.052 mm2 of area to support both encryption and decryption with 311 Mbps throughput. By making effective use of the SPN parallel feature, the throughput can be boosted up to 2.6 Gbps for a high-speed implementation whose size is 21.3 Kgates.