A Compact Rijndael Hardware Architecture with S-Box Optimization
ASIACRYPT '01 Proceedings of the 7th International Conference on the Theory and Application of Cryptology and Information Security: Advances in Cryptology
Efficient Rijndael Encryption Implementation with Composite Field Arithmetic
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Two Methods of Rijndael Implementation in Reconfigurable Hardware
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Integrated Design of AES (Advanced Encryption Standard) Encrypter and Decrypter
ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Configuration Sharing to Reduce Reconfiguration Overhead Using Static Partial Reconfiguration
IEICE - Transactions on Information and Systems
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Hardware implementations of cryptography face increasingly more stringent demands for lower cost and greater computational power. In order to meet those demands,mor e efficient approaches to implementations are needed. This paper presents detailed studies of MixColumn and InvMixColumn operations used in Advanced Encryption Standard with aim at their hardware implementations in constrained environments. Our studies are supported by mathematical analysis of both transformations and lead to efficient serial and parallel decompositions. Furthermore, deeper resource sharing is demonstrated at word-,byte- and bit-level. All derived architectures are evaluated using popular low-cost field-programmable gate arrays. Application of proposed methods resulted in reduction of reconfigurable logic area of the complete cipher by up to 20%.