A 2 Gb/s balanced AES crypto-chip implementation
Proceedings of the 14th ACM Great Lakes symposium on VLSI
High-speed VLSI architectures for the AES algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A generic characterization of the overheads imposed by IPsec and associated cryptographic algorithms
Computer Networks: The International Journal of Computer and Telecommunications Networking
Design and realization of a new signal security system for multimedia data transmission
EURASIP Journal on Applied Signal Processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Inv mix column decomposition and multilevel resource sharing in AES implementations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NanoCMOS-molecular realization of rijndael
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
A systematic evaluation of compact hardware implementations for the rijndael s-box
CT-RSA'05 Proceedings of the 2005 international conference on Topics in Cryptology
Secure and efficient AES software implementation for smart cards
WISA'04 Proceedings of the 5th international conference on Information Security Applications
Small size, low power, side channel-immune AES coprocessor: design and synthesis results
AES'04 Proceedings of the 4th international conference on Advanced Encryption Standard
Secure AES hardware module for resource constrained devices
ESAS'04 Proceedings of the First European conference on Security in Ad-hoc and Sensor Networks
Position paper: cloud-based performance testing: issues and challenges
Proceedings of the 2013 international workshop on Hot topics in cloud services
Hi-index | 0.00 |
This paper proposed a method to integrate the AES encrypter and the AES decrypter into a full functional AES crypto-engine. This method can make it a very low-complexity architecture,especially in saving the hardware resource in implementing the AES (Inv)SubBytes module and (Inv)Mixcolumns module, etc. Most designed modules can be used for both AES encryption and decryption. Besides, the architecture can still deliver a high data rate in both en/decryption operations. The proposed architecture is suited for hardware-critical applications, such as smart card, PDA, and mobile phone, etc.