An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The Design of Rijndael
CT-RSA 2001 Proceedings of the 2001 Conference on Topics in Cryptology: The Cryptographer's Track at RSA
An ASIC Implementation of the AES SBoxes
CT-RSA '02 Proceedings of the The Cryptographer's Track at the RSA Conference on Topics in Cryptology
2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Rijndael FPGA Implementations Utilising Look-Up Tables
Journal of VLSI Signal Processing Systems
Integrated Design of AES (Advanced Encryption Standard) Encrypter and Decrypter
ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
A highly efficient AES cipher chip
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
AES Efficient implementation for extensible firmware interface
MS'06 Proceedings of the 17th IASTED international conference on Modelling and simulation
A new methodology to implement the AES algorithm using partial and dynamic reconfiguration
Integration, the VLSI Journal
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We present a balanced 2 Gb/s en-/decryption ASIC realization of the AES algorithm that supports all standard operation modes and key lengths. Rather than optimizing only for throughput, special care is taken to balance the more involved decryption path with that of the encryption path using a number of high-level architectural and register transfer level optimizations. The fabricated en-/decryption core requires an active area of only 3.56 mm2 (less than 120,000 gate equivalents) in a modest 0.25 µm CMOS technology.