A highly efficient AES cipher chip

Authors:
Chih-Pin Su;Tsung-Fu Lin;Chih-Tsun Huang;Cheng-Wen Wu
Affiliations:
National Tsing Hua University, Hsinchu, Taiwan, ROC;National Tsing Hua University, Hsinchu, Taiwan, ROC;National Tsing Hua University, Hsinchu, Taiwan, ROC;National Tsing Hua University, Hsinchu, Taiwan, ROC
Venue:
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Year:
2003

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Abstract

We present an efficient hardware implementation of the AES (Advanced Encryption Standard) algorithm, with key expansion capability. Instead of the widely used table-lookup implementation of S-box, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64% and is easily pipelined to achieve high throughput rate. Using a typical 0.25μm CMOS technology, the throughput rate is 2.977 Gbps for 128-bit keys, 2.510 Gbps for 192-bit keys, and 2.169 Gbps for 256-bit keys with a 250MHz clock. Testability of the design is also considered. The area of the core circuit is about 1,279 x 1,271μm2.