The Design of Rijndael
Efficient Software Implementation of AES on 32-Bit Platforms
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
High throughput, parallelized 128-bit AES encryption in a resource-limited FPGA
Proceedings of the fifteenth annual ACM symposium on Parallel algorithms and architectures
AES and the cryptonite crypto processor
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Efficient AES implementations for ARM based platforms
Proceedings of the 2004 ACM symposium on Applied computing
A 2 Gb/s balanced AES crypto-chip implementation
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Accelerating AES using instruction set extensions for elliptic curve cryptography
ICCSA'05 Proceedings of the 2005 international conference on Computational Science and Its Applications - Volume Part II
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As one of the most significant cryptographic algorithms, the Advanced Encryption Standard (AES) will play a central role in securing information exchange and communication in the next decade. Though its basic elements are fully defined in terms of functionality, AES requires the best exploitation of implementation in order to achieve optimum performance on specific architectures. This paper focuses on Extensible Firmware Interface (EFI) which is being applied as the next generation firmware technology. We present a new AES usage model within framework of EFI/Tiano based on IA-32 platform, which is an efficient implementation with its improved performance.