Efficient AES implementations on ASICs and FPGAs

Authors:
Norbert Pramstaller;Stefan Mangard;Sandra Dominikus;Johannes Wolkerstorfer
Affiliations:
Institute for Applied Information Processing and Communications (IAIK), Graz University of Technology, Graz, Austria;Institute for Applied Information Processing and Communications (IAIK), Graz University of Technology, Graz, Austria;Institute for Applied Information Processing and Communications (IAIK), Graz University of Technology, Graz, Austria;Institute for Applied Information Processing and Communications (IAIK), Graz University of Technology, Graz, Austria
Venue:
AES'04 Proceedings of the 4th international conference on Advanced Encryption Standard
Year:
2004

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Abstract

In this article, we present two AES hardware architectures: one for ASICs and one for FPGAs. Both architectures utilize the similarities of encryption and decryption to provide a high throughput using only a relatively small area. The presented architectures can be used in a wide range of applications. The architecture for ASIC implementations is suited for full-custom as well as for semi-custom design flows. The architecture for the FPGA implementation does not require on-chip block RAMs and can therefore even be used for low-cost FPGAs.