Review of hardware architectures for advanced encryption standard implementations considering wireless sensor networks

Authors:
Panu Hämäläinen;Marko Hännikäinen;Timo D. Hämäläinen
Affiliations:
Nokia Technology Platforms,WiWLAN SF, Tampere, Finland;Tampere University of Technology, Institute of Digital and Computer Systems, Tampere, Finland;Tampere University of Technology, Institute of Digital and Computer Systems, Tampere, Finland
Venue:
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Year:
2007

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Abstract

Wireless Sensor Networks (WSN) are seen as attractive solutions for various monitoring and controlling applications, a large part of which require cryptographic protection. Due to the strict cost and power consumption requirements, their cryptographic implementations should be compact and energy-efficient. In this paper, we survey hardware architectures proposed for Advanced Encryption Standard (AES) implementations in low-cost and low-power devices. The survey considers both dedicated hardware and specialized processor designs. According to our review, currently 8-bit dedicated hardware designs seem to be the most feasible solutions for embedded, low-power WSN nodes. Alternatively, compact special functional units can be used for extending the instruction sets of WSN node processors for efficient AES execution.