Compact hardware design of Whirlpool hashing core
Proceedings of the conference on Design, automation and test in Europe
Multi-gigabit GCM-AES Architecture Optimized for FPGAs
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Power and EM Attacks on Passive $13.56\,\textrm{MHz}$ RFID Devices
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Ultra-Lightweight Implementations for Smart Devices --- Security for 1000 Gate Equivalents
CARDIS '08 Proceedings of the 8th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
KATAN and KTANTAN -- A Family of Small and Efficient Hardware-Oriented Block Ciphers
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
A randomized countermeasure against parasitic adversaries in wireless sensor networks
IEEE Journal on Selected Areas in Communications - Special issue on simple wireless sensor networking solutions
PRINTcipher: a block cipher for IC-printing
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
256 bit standardized crypto for 650 GE: GOST revisited
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
Hummingbird: ultra-lightweight cryptography for resource-constrained devices
FC'10 Proceedings of the 14th international conference on Financial cryptograpy and data security
SAC'10 Proceedings of the 17th international conference on Selected areas in cryptography
Pushing the limits: a very compact and a threshold implementation of AES
EUROCRYPT'11 Proceedings of the 30th Annual international conference on Theory and applications of cryptographic techniques: advances in cryptology
A cryptographic processor for low-resource devices: canning ECDSA and AES like sardines
WISTP'11 Proceedings of the 5th IFIP WG 11.2 international conference on Information security theory and practice: security and privacy of mobile devices in wireless communication
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Piccolo: an ultra-lightweight blockcipher
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Very compact hardware implementations of the blockcipher CLEFIA
SAC'11 Proceedings of the 18th international conference on Selected Areas in Cryptography
KLEIN: a new family of lightweight block ciphers
RFIDSec'11 Proceedings of the 7th international conference on RFID Security and Privacy
Attacking an AES-Enabled NFC tag: implications from design to a real-world scenario
COSADE'12 Proceedings of the Third international conference on Constructive Side-Channel Analysis and Secure Design
On area, time, and the right trade-off
ACISP'12 Proceedings of the 17th Australasian conference on Information Security and Privacy
How far should theory be from practice?: evaluation of a countermeasure
CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
Error detecting AES using polynomial residue number systems
Microprocessors & Microsystems
Putting together what fits together: grÆstl
CARDIS'12 Proceedings of the 11th international conference on Smart Card Research and Advanced Applications
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The Advanced Encryption Standard (AES) algorithm has become the default choice for various security services in numerous applications. In this paper we present an AES encryption hardware core suited for devices in which low cost and low power consumption are desired. The core constitutes of a novel 8-bit architecture and supports encryption with 128-bit keys. In a 0.13 ìm CMOS technology our area optimized implementation consumes 3.1 kgates. The throughput at the maximum clock frequency of 153 MHz is 121 Mbps, also in feedback encryption modes. Compared to previous 8-bit implementations, we achieve significantly higher throughput with corresponding area. The energy consumption per processed block is also lower.