Handbook of Applied Cryptography
Handbook of Applied Cryptography
A compact FPGA implementation of the hash function whirlpool
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Finding collisions in the full SHA-1
CRYPTO'05 Proceedings of the 25th annual international conference on Advances in Cryptology
How to break MD5 and other hash functions
EUROCRYPT'05 Proceedings of the 24th annual international conference on Theory and Applications of Cryptographic Techniques
Efficient architecture and hardware implementation of the Whirlpool hash function
IEEE Transactions on Consumer Electronics
Isolated WDDL: A Hiding Countermeasure for Differential Power Analysis on FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Compact ASIC Architectures for the 512-Bit Hash Function Whirlpool
Information Security Applications
Hardware evaluation of the stream cipher-based hash functions RadioGatún and irRUPT
Proceedings of the Conference on Design, Automation and Test in Europe
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Weaknesses have recently been found in the widely used cryptographic hash functions SHA-1 and MD5. A potential alternative for these algorithms is the Whirlpool hash function, which has been standardized by ISO/IEC and evaluated in the European research project NESSIE. In this paper we present a Whirlpool hashing hardware core suited for devices in which low cost is desired. The core constitutes of a novel 8-bit architecture that allows compact realizations of the algorithm. In the Xilinx Virtex-II Pro XC2VP40 FPGA, our implementation consumes 376 slices and achieves the throughput of 81.5 Mbit/s. The resource utilization of our design is one fourth of the smallest Whirlpool implementation presented to date.