Handbook of Applied Cryptography
Handbook of Applied Cryptography
Compact hardware design of Whirlpool hashing core
Proceedings of the conference on Design, automation and test in Europe
Merged computation for Whirlpool hashing
Proceedings of the conference on Design, automation and test in Europe
WISA'07 Proceedings of the 8th international conference on Information security applications
Improving SHA-2 hardware implementations
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Finding collisions in the full SHA-1
CRYPTO'05 Proceedings of the 25th annual international conference on Advances in Cryptology
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In the next years, new hash function candidates will replace the old MD5 and SHA-1 standards and the current SHA-2 family. The hash algorithms RadioGatún and irRUPT are potential successors based on a stream structure, which allows the achievement of high throughputs (particularly with long input messages) with minimal area occupation. In this paper, several hardware architectures of the two above mentioned hash algorithms have been investigated. The implementation on ASIC of RadioGatún with a word length of 64 bits shows a complexity of 46k gate equivalents (GE) and reaches 5.7 Gbps throughput with a 3 · 64-bit input message. The same design approaches 120 Gbps on ASIC with long input messages (63.4 Gbps on a Virtex-4 FPGA with 2.9 kSlices). On the other hand, the irRUPT core turns out to be the most compact circuit (only 5.8 kGE on ASIC, and 370 Slices on FPGA) achieving 2.4 Gbps (with long input messages) on ASIC, and 1.1Gbps on FPGA.