The Design of Rijndael
On the Construction of Block Ciphers Provably Secure and Not Relying on Any Unproved Hypotheses
CRYPTO '89 Proceedings of the 9th Annual International Cryptology Conference on Advances in Cryptology
Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Ultra-Lightweight Implementations for Smart Devices --- Security for 1000 Gate Equivalents
CARDIS '08 Proceedings of the 8th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
Secure Hardware Implementation of Non-linear Functions in the Presence of Glitches
Information Security and Cryptology --- ICISC 2008
KATAN and KTANTAN -- A Family of Small and Efficient Hardware-Oriented Block Ciphers
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Pushing the limits: a very compact and a threshold implementation of AES
EUROCRYPT'11 Proceedings of the 30th Annual international conference on Theory and applications of cryptographic techniques: advances in cryptology
Threshold implementations against side-channel attacks and glitches
ICICS'06 Proceedings of the 8th international conference on Information and Communications Security
The 128-bit blockcipher CLEFIA
FSE'07 Proceedings of the 14th international conference on Fast Software Encryption
On area, time, and the right trade-off
ACISP'12 Proceedings of the 17th Australasian conference on Information Security and Privacy
PRINCE: a low-latency block cipher for pervasive computing applications
ASIACRYPT'12 Proceedings of the 18th international conference on The Theory and Application of Cryptology and Information Security
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The 128-bit blockcipher CLEFIA is known to be highly efficient in hardware implementations. This paper proposes very compact hardware implementations of CLEFIA-128. Our implementations are based on novel serialized architectures in the data processing block. Three types of hardware architectures are implemented and synthesized using a 0.13 $#956;m standard cell library. In the smallest implementation, the area requirements are only 2,488 GE, which are about half of the previous smallest implementation as far as we know. Furthermore, only additional 116 GE enable to support decryption.