VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
IEEE Transactions on Computers
Introduction to finite fields and their applications
Introduction to finite fields and their applications
An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
In How Many Ways Can You Write Rijndael?
ASIACRYPT '02 Proceedings of the 8th International Conference on the Theory and Application of Cryptology and Information Security: Advances in Cryptology
Rijndael FPGA Implementations Utilising Look-Up Tables
Journal of VLSI Signal Processing Systems
A Highly Regular and Scalable AES Hardware Architecture
IEEE Transactions on Computers
The happy marriage of architecture and application in next-generation reconfigurable systems
Proceedings of the 1st conference on Computing frontiers
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A 10-Gbps full-AES crypto design with a twisted BDD S-box architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improving Memory Encryption Performance in Secure Processors
IEEE Transactions on Computers
The cryptanalysis of the AES – a brief survey
AES'04 Proceedings of the 4th international conference on Advanced Encryption Standard
Efficient AES implementations on ASICs and FPGAs
AES'04 Proceedings of the 4th international conference on Advanced Encryption Standard
AES'04 Proceedings of the 4th international conference on Advanced Encryption Standard
A high-throughput low-cost AES processor
IEEE Communications Magazine
A novel AES cryptographic core highly resistant to differential power analysis attacks
Proceedings of the 21st annual symposium on Integrated circuits and system design
The secure DAES design for embedded system application
EUC'07 Proceedings of the 2007 conference on Emerging direction in embedded and ubiquitous computing
Single- and multi-core configurable AES architectures for flexible security
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An iterative logarithmic multiplier
Microprocessors & Microsystems
A compact AES core with on-line error-detection for FPGA applications with modest hardware resources
Microprocessors & Microsystems
Reconfigurable and parallelized network coding decoder for VANETs
Mobile Information Systems
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In this article, we present a FPGA-based reconfigurable system for the advanced encryption standard (AES) algorithm. This proposed design, called diversified AES (DAES), has the variations of four parameters: the field irreducible polynomial, the affine transformation in the SubBytes, the offsets in the ShiftRows, and the polynomial in the MixColumns. The advantage of such variations in the AES system is that they increase the strength regarding internal or external attacks. We also use straightforward architecture - look-up tables - for encryption and decryption to lead this system simple and high-speed using field programmable gate arrays (FPGAs).