VLSI Implementation of a Low-Power Antilogarithmic Converter
IEEE Transactions on Computers
CMOS VLSI Implementation of a Low-Power Logarithmic Converter
IEEE Transactions on Computers
Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition
IEEE Transactions on Computers
Computer Architecture, Fourth Edition: A Quantitative Approach
Computer Architecture, Fourth Edition: A Quantitative Approach
Reconfigurable system for high-speed and diversified AES using FPGA
Microprocessors & Microsystems
The Journal of Supercomputing
FPGA-oriented HW/SW implementation of the MPEG-4 video decoder
Microprocessors & Microsystems
An efficient CSA architecture for montgomery modular multiplication
Microprocessors & Microsystems
Multiplierless and fully pipelined JPEG compression soft IP targeting FPGAs
Microprocessors & Microsystems
IEEE Transactions on Computers
Testing digital low-pass filters using oscillation-based test
Microprocessors & Microsystems
Design and evaluation of a hardware/software FPGA-based system for fast image processing
Microprocessors & Microsystems
Experiences with a FPGA-based Reed/Solomon-encoding coprocessor
Microprocessors & Microsystems
On the design of reconfigurable multipliers for integer and Galois field multiplication
Microprocessors & Microsystems
An 8-bit systolic AES architecture for moderate data rate applications
Microprocessors & Microsystems
Parameterized MAC unit generation for a scalable embedded DSP core
Microprocessors & Microsystems
A high performance ECC hardware implementation with instruction-level parallelism over GF(2163)
Microprocessors & Microsystems
Logarithmic multiplier in hardware implementation of neural networks
ICANNGA'11 Proceedings of the 10th international conference on Adaptive and natural computing algorithms - Volume Part I
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Digital signal processing algorithms often rely heavily on a large number of multiplications, which is both time and power consuming. However, there are many practical solutions to simplify multiplication, like truncated and logarithmic multipliers. These methods consume less time and power but introduce errors. Nevertheless, they can be used in situations where a shorter time delay is more important than accuracy. In digital signal processing, these conditions are often met, especially in video compression and tracking, where integer arithmetic gives satisfactory results. This paper presents a simple and efficient multiplier with the possibility to achieve an arbitrary accuracy through an iterative procedure, prior to achieving the exact result. The multiplier is based on the same form of number representation as Mitchell's algorithm, but it uses different error correction circuits than those proposed by Mitchell. In such a way, the error correction can be done almost in parallel (actually this is achieved through pipelining) with the basic multiplication. The hardware solution involves adders and shifters, so it is not gate and power consuming. The error summary for operands ranging from 8 bits to 16 bits indicates a very low relative error percentage with two iterations only. For the hardware implementation assessment, the proposed multiplier is implemented on the Spartan 3 FPGA chip. For 16-bit operands, the time delay estimation indicates that a multiplier with two iterations can work with a clock cycle more than 150MHz, and with the maximum relative error being less than 2%.